(1) Field of the Invention
The present invention relates to semiconductor devices, and more specifically to a process for fabricating high density, dynamic random access memory, (DRAM), devices
(2) Description of Prior Art
The major objective of the semiconductor industry, in producing DRAM devices, is to continually increase the density of the DRAM product, while still maintaining, or lowering the cost of these specific devices. The basic DRAM memory cell is usually comprised of a transfer gate transistor and a connected capacitor. Charges are stored in the capacitor section of the DRAM, and are accessed via the transfer gate transistor. The ability to densely pack storage cells, while still maintaining sufficient stored charge, is a function of the type and structure of the capacitor section of the DRAM. Two iterations of capacitors are presently being manufactured. A trench capacitor, in which charge is stored vertically in a structure fabricated by etching a deep trench in a substrate, has found use where high DRAM densities are desired. This type of capacitor, although eventually needed for the higher density DRAMS, is however costly to fabricate, regarding the trench etching, trench filling and planarization processing. A second type of capacitor used in the DRAM technology is the stacked capacitor cell, (STC). In this design two conductive layers, such as polycrystalline silicon, are placed over a section of the transfer gate transistor, with a dielectric layer sandwiched between the polycrystalline layers. The STC iteration has been used extensively in the industry, with emphasis placed on reducing the cost, while still increasing DRAM chip densities.
In order to successfully increase DRAM densities efforts have been directed to reducing specific device geometries. This has been accomplished via advantages in the photolithographic discipline, where more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have allowed sub-micron chip features to be routinely achieved. Other semiconductor device fabrication disciplines, such as reactive ion etching, (RIE), as well as ion implantation, (I/I), and low pressure chemical vapor deposition, (LPCVD), have also contributed to the successful objective of decreasing specific device geomotries. However with the trend to more sophisticated semiconductor equipment and processes, the ability to maintain or reduce cost becomes more difficult.
The objective of cost reduction has been addressed by the DRAM industry in the form of mask reduction. That is attempting to fabricate the desired DRAM design, while using fewer, costly photolithographic steps. Gilgen, et al, in U.S. Pat. No. 5,134,085, describe a DRAM process in which significant reductions in photomasking steps have occurred. However they still show a "split polysilicon" process, in which the polysilicon used for the gate structure for P channel devices, is patterned using one photo step, while another photo step is needed to pattern the capacitor plate for the STC structure. This step occurred after fabrication of the polysilicon, n gates used for the N channel devices. The ability to fabricate the gate structures at different points of the process allowed for the creation of the lightly doped, as well as the more highly doped, source and drain regions to be obtained without the use of photolithographic processing, thus reducing the cost of the DRAM chip. This patent, though partially successsful in reducing photomasking steps compromises P channel performance by an intentional undercut of the polysilicon gate structure, designed to reduce source to gate overlap capacitance. However this undercut increases resistance and decreases the performance of the P channel device.
This invention will describe a DRAM process with a significant reduction in photolithographic steps, while still maintaining superior P channel performance. In addition this invention will describe a fabrication method used to obtain self aligned bit line, and storage node contacts, offering performance improvements.